1. Technical Field
Various embodiments of the present invention relate to a semiconductor apparatuses. In particular, certain embodiments relate to a semiconductor memory apparatus and a memory system including the same.
2. Related Art
A typical memory system includes a memory controller, and a semiconductor memory apparatus such as a dynamic random access memory (DRAM) device. In some systems, a processor also performs functions of a memory controller. A semiconductor memory apparatus is usually arranged on a memory module, and modules are coupled to a memory controller through a memory interface. For example, the memory interface may include a chip select line, an address bus line, a command signal line, and a data bus line.
In such a memory system, the memory controller is mounted on a printed circuit board and the semiconductor memory apparatus is mounted on the memory module. The memory module is coupled to the printed circuit board through a connector.
Such a semiconductor memory apparatus may be a memory array having a cell table. These cells may include capacitors substantially maintaining charges and store one or more data bits based on the configuration of the semiconductor memory apparatus. Furthermore, each semiconductor memory apparatus is referred to as a semiconductor chip in the printed circuit board.
FIGS. 1 and 2 are diagrams illustrating the configuration of a typical memory system. As illustrated in FIGS. 1 and 2, a general memory system 100 may include a memory controller 110 and a semiconductor memory apparatus 120 driven in response to command/address signals from the memory controller 110, and a general memory system 200 may include a memory controller 210 and a semiconductor memory apparatus 220 driven in response to command/address signals from the memory controller 210. The semiconductor memory apparatus 120 and 220 may include two semiconductor chips chip1 and chip2 integrated therein as illustrated in FIG. 1 or one semiconductor chip chip1 integrated therein as illustrated in FIG. 2.
As illustrated in FIG. 1, the semiconductor memory apparatus 120 may include two semiconductor chips chip1 and chip2 with a capacity of 4 Gb to achieve the total capacity of 8 Gb. The configuration as illustrated in FIG. 1 will be referred to as an 8 Gb double die package (DDP). Here, the DDP denotes a semiconductor memory apparatus including two or more semiconductor chips.
As illustrated in FIG. 2, the semiconductor memory apparatus 220 may include one semiconductor chip chip1 with a capacity of 8 Gb which is substantially equal to that of the semiconductor memory apparatus 120 illustrated in FIG. 1. The configuration as illustrated in FIG. 2 will be referred to as an 8 Gb single die package (SDP). Here, the SDP denotes a semiconductor memory apparatus including one semiconductor chip.
As described above, in FIG. 1, the two semiconductor chips chip1 and chip2 with a capacity of 4 Gb are stacked to form the semiconductor memory apparatus 120, resulting in an increase in the capacity of the semiconductor memory apparatus 120 but in the reduction in the integration degree of the memory system 100.
Meanwhile, in FIG. 2, the semiconductor memory apparatus 220 includes one semiconductor chip chip1 with a capacity of 8 Gb, resulting in the improvement of the integration degree of the memory system as compared with FIG. 1. However, since one address buffer for an additional address ADD<16> is provided as well, a separate control circuit for controlling an additional address signal is further necessary, resulting in an increase in the size of the memory system 200.
Therefore, the typical memory systems 100 and 200 should use the semiconductor memory apparatus 120 illustrated in FIG. 1 in order to increase the capacity of a semiconductor memory apparatus while abandoning the integration degree of the memory system, and should use the semiconductor memory apparatus 220 illustrated in FIG. 2 in order to increase the capacity of a semiconductor memory apparatus while satisfying the integration degree of the memory system. Therefore, since the typical memory system should be designed again as the memory system 200 illustrated in FIG. 2 in order to satisfy the integration degree in the state in which the memory system 100 illustrated in FIG. 1 is designed in advance, the time and the manufacturing cost increase.
Furthermore, when the typical memory system includes two or more semiconductor chips integrated therein, since it may not be possible to estimate in advance a semiconductor chip which will operate, current may be unnecessarily consumed.